1. Technical Field
The present invention relates to a low drop out regulator (LDO), and more particularly, to an LDO having a phase margin compensation means capable of minimizing a change in output voltage of the LDO due to external environment factors by compensating for a phase margin in a circuit and a phase margin compensation method using the LDO.
2. Description of the Related Art
In designing an electronic circuit system, one of the important decisions relates to a determination of a power supply voltage level. Optimized power supply voltage levels are different for each system. Therefore, a need exists for a circuit converting external power supply voltage into internal power supply voltage having a specific value. A circuit used for the above purpose is a regulator. In particular, the regulator having a small difference between input voltage and output voltage small is referred to as low drop out (LDO). The above-mentioned LDO is often used in a circuit having a small difference between the input voltage and the output voltage. Performance indexes evaluating the LDO may include “Line Regulation,” “Load Regulation,” “Power Supply Rejection Ratio (PSRR),” “Efficiency,” and the like. The performance indexes described above may be represented by the following Equation.
      Line_Regulation    =                  Δ        ⁢                                  ⁢        Vo                    Δ        ⁢                                  ⁢        Vi                  Load_Regulation    =                  Δ        ⁢                                  ⁢        Vo                    Δ        ⁢                                  ⁢        Io                        P      ⁢                          ⁢      S      ⁢                          ⁢      R      ⁢                          ⁢      R        =                  Vo        ,        ripple                    Vi        ,        ripple                  Efficiency    =                            Io          ·          Vo                                      (                          Io              +              Iq                        )                    ⁢          Vi                    ×      100      
As can be appreciated from the above Equation, the equation related to the LDO is related to how stably the characteristics of the output voltage appear. That is, good line regulation may correspond to a case in which a change in the output voltage with respect to a change in the input voltage is small and good load regulation may correspond to a case in which the change in the output voltage is small even though load current is changed.
In addition, good PSRR characteristics may correspond to a case in which a ripple minimally appears in an output even though an input ripple is present and good efficiency may correspond to a case in which quiescent current (Iq) is small and the difference between the input voltage and the output voltage is small if it is assumed that Vo<Vi. That is, as can be appreciated from the above Equations, making the output voltage so as to be less affected by external environment may be the most important role of the LDO.
FIG. 1 is a diagram schematically showing a configuration of a general LDO.
As shown in FIG. 1, a general LDO 100 includes several parameters such as an operational amplifier 101, a transistor (FET) 102, resistors 103 and 104, and the like, wherein the parameters are set so that the LDO 100 indicate the accurate output voltage and is operated in a stable region. In particular, the LDO 100 is a circuit having high oscillation possibility and thus, a gain margin and a phase margin need to be carefully checked. Here, the gain margin and the phase margin will be described additionally.
FIG. 2 is a diagram graphically describing the gain margin and the phase margin.
As shown in FIG. 2, the phase margin (see FIG. 2B) means a difference between a point having a gain of 0 and a point having a phase changed of 180° at a frequency having a gain of 0. In a feedback system, changing a phase of 180° means that a circuit may be unstable accordingly. Therefore, as the difference is increased, it may be determined that the phase margin is present, which means that the circuit is stable accordingly. FIG. 2A shows the gain margin.
FIG. 3 is a diagram showing an example of a frequency response of the LDO.
Referring to FIG. 3, the frequency response of the system is determined by pole and zero, such that the stability and instability of the system are determined. The phase margin at a frequency unity gain frequency (UFG) having a gain of 0 dB is confirmed. When the phase margin is less than a reference, the system may be considered to be in an unstable region and when the phase margin is higher than a reference, the system can be considered to be operated in a stable region. The reference of the phase margin is generally considered to be about 60°. That is, when the phase margin is designed to be 60° or more, the system may be stable and may be beyond the risk of oscillation.